w = write r = read
1000 porta 1001 reserved 1002 pioc w 1....... staf: strobe a flag, set at active edge of stra pin/inactive w .1...... stai: hardware interrupt request when STAF=1 w ..1..... cwom: port c open-drain w ...1.... hnds: handshake/simple strobe mode w ....1... oin: output/input handshake select w .....1.. pls: STRB pulse/level active w ......1. ega: rising/falling edge select for STRA w .......1 invb: STRB active high/low 1003 portc 1004 portb 1005 portcl 1006 reserved 1007 ddrc: data direction register for port c (1=output) 1008 portd (b0..b5) rw 1....... mode0 or boot: strb rw 1....... mode1 or test: r/w rw .1...... mode0 or boot: stra rw .1...... mode1 or test: as rw ..1..... pd5/ss* rw ...1.... pd4/sck rw ....1... pd3/mosi rw .....1.. pd2/miso rw ......1. pd1/txd rw .......1 pd0/rxd 1009 ddrd: data direction register for port d (1=output) (b0..b5) 100A porte: port e data register 100B cforc: timer compare force register w 1....... foc1 w .1...... foc2 w ..1..... foc3 w ...1.... foc4 w ....1... foc5 w 11111111 force compare(s) w .....xxx reserved 100C oc1m: set bits to enable oc1 to control corresponding pin(s) of port a w 1....... oc1m7 w .1...... oc1m6 w ..1..... oc1m5 w ...1.... oc1m4 w ....1... oc1m3 w .....xxx reserved w 11111111 force compare(s) 100D oc1d: if oc1mx is set, data in oc1dx is output to port a bit-x on successful oc1 compares w 1....... oc1d7 w .1...... oc1d6 w ..1..... oc1d5 w ...1.... oc1d4 w ....1... oc1d3 w .....xxx reserved w 11111111 force compare(s) 100E tcnt: timer counter register 1010 tic1: timer input capture register 1012 tic2: timer input capture register 1014 tic3: timer input capture register 1016 toc1: timer output compare register 1018 toc2: timer output compare register 101A toc3: timer output compare register 101C toc4: timer output compare register 101E toc5: timer output compare register 1020 tctl1: timer control register 1 w 1....... om2 w .1...... ol2 w ..1..... om3 w ...1.... ol3 w ....1... om4 w .....1.. ol4 w ......1. om5 w .......1 ol5 for all pairs: w 00...... timer disconnected from output pin logic w 01...... ocx output line: toggle w 10...... ocx output line: 0 w 11...... ocx output line: 1 1021 tctl2: timer control register 2 w xx...... reserved w ..1..... edg1b w ...1.... edg1a w ....1... edg2b w .....1.. edg2a w ......1. edg3b w .......1 edg3a for all pairs: w ..00.... capture: disabled w ..01.... capture: on rising edge only w ..10.... capture: on falling edge only w ..11.... capture: on any edge 1022 tmsk1: main timer interrupt mask reg 1 w 1....... oc1l: output compare 1 interrupt enable w .1...... oc2l: output compare 2 interrupt enable w ..1..... oc3l: output compare 3 interrupt enable w ...1.... oc4l: output compare 4 interrupt enable w ....1... oc5l: output compare 5 interrupt enable w .....1.. ic1l: input compare 1 interrupt enable w ......1. ic2l: input compare 2 interrupt enable w .......1 ic3l: input compare 3 interrupt enable 1023 tflg1: main timer interrupt flag reg 1 w 1....... oc1f: clear output compare flag 1 w .1...... oc2f: clear output compare flag 2 w ..1..... oc3f: clear output compare flag 3 w ...1.... oc4f: clear output compare flag 4 w ....1... oc5f: clear output compare flag 5 w .....1.. ic1f: clear input capture flag 1 w ......1. ic2f: clear input capture flag 2 w .......1 ic3f: clear input capture flag 3 1024 tmsk2: misc timer interrupt mask reg 2 w 1....... toi: timer overflow interrupt enable w .1...... rtii: interrupt enable w ..1..... paovi: pulse accumulator overflow interrupt enable w ...1.... paii: pulse accumulator input interrupt enable/disable w ....xx.. reserved w ......00 pr1,pr0: timer prescale factor 1 w ......01 pr1,pr0: timer prescale factor 4 w ......10 pr1,pr0: timer prescale factor 8 w ......11 pr1,pr0: timer prescale factor 16 1025 tflg2: misc timer interrupt flag reg 2 w 1....... tof: clear timer overflow flag w .1...... rtif: clear real time (periodic) interrupt flag w ..1..... paovf: clear pulse accumulator overflow flag w ...1.... paif: clear paif pulse accumulator input edge flag w ....xxxx reserved 1026 pactl: pulse accumulator control register w 1....... ddra7: data direction for port a bit7 is output/input w .1...... paen: enable/disable pulse accumulator system enable w ..1..... pamod: pulse acc mode: gated time accumulation/event counter w ...1.... pedge: pulse acc edge ctrl: rising/falling edges w ....xx.. reserved w ......00 rtr1,rtr0: interrupt rate divide by 2^13 w ......01 rtr1,rtr0: interrupt rate divide by 2^14 w ......10 rtr1,rtr0: interrupt rate divide by 2^15 w ......11 rtr1,rtr0: interrupt rate divide by 2^16 1027 pacnt: pulse accumulator count register 1028 spcr: spi control register w 1....... spie: spi interrupt enable w .1...... spe: spi system enable w ..1..... dwom: port d: open-drain/normal w ...1.... mstr: master/slave mode w ....1... cpol: clock polarity w .....1.. cpha: clock phase w ......00 spr1,spr0: spi e-clock divided by 2 w ......01 spr1,spr0: spi e-clock divided by 4 w ......10 spr1,spr0: spi e-clock divided by 8 w ......11 spr1,spr0: spi e-clock divided by 16 1029 spsr: spi status register r 1....... spif: spi interrupt request r .1...... wcol: write collision status flag r ...1.... modf: spi mode error interrupt status flag r ..x.xxxx reserved 102A spdr: spi data register 102B baud: sci baud rate control register w 1....... tclr: clear baud counter chain (test only) w .x...... reserved w ..00.... scp1,scp0: serial prescaler select: divide e-clock by 1 w ..01.... scp1,scp0: serial prescaler select: divide e-clock by 2 w ..10.... scp1,scp0: serial prescaler select: divide e-clock by 4 w ..11.... scp1,scp0: serial prescaler select: divide e-clock by 13 w ....1... rckb: sci baud rate clock test (test only) w .....000 scr2,scr1,scr0: prescaler output divide by 1 w .....001 scr2,scr1,scr0: prescaler output divide by 2 w .....010 scr2,scr1,scr0: prescaler output divide by 4 w .....011 scr2,scr1,scr0: prescaler output divide by 8 w .....100 scr2,scr1,scr0: prescaler output divide by 16 w .....101 scr2,scr1,scr0: prescaler output divide by 32 w .....110 scr2,scr1,scr0: prescaler output divide by 64 w .....111 scr2,scr1,scr0: prescaler output divide by 128 102C sccr1: sci control register 1 w 1....... r8: receive bit 8 w .1...... t8: transmit bit 8 w ...1.... m: ninth data bit w ....1... wake: wake up by address mark/idle line (msb/no low) w ..x..xxx reserved 102D sccr2: sci control register 2 w 1....... tie: transmit interrupt enable w .1...... tcie: transmit complete interrupt enable w ..1..... rie: receiver interrupt enable w ...1.... ilie: enable/disable idle line interrupts w ....1... te: transmitter enable (toggle to queue idle character) w .....1.. re: receiver enable on/off w ......1. rwu: receiver asleep/normal w .......1 sbk: send break 102E scsr: sci status register r 1....... tdre: transmit data register empty flag r .1...... tc: transmit complete flag r ..1..... rdrf: receive data register full flag r ...1.... idle: idle line detected flag r ....1... or: over-run error flag r .....1.. nf: noise error flag r ......1. fe: framing error flag r .......x reserved 102F scdr: sci data register 1030 adctl: a/d control/status register r 1....... ccf: conversions complete flag (sets after fourth conversion) rw .x...... reserved w ..1..... scan: convert continuously/4 conversions and stop w ...1.... mult: convert four channel group/single channel rw ....0000 cd,cc,cb,ca: ad0 port e bit0 rw ....0001 cd,cc,cb,ca: ad1 port e bit1 rw ....0010 cd,cc,cb,ca: ad2 port e bit2 rw ....0011 cd,cc,cb,ca: ad3 port e bit3 rw ....0100 cd,cc,cb,ca: ad4 port e bit4 rw ....0101 cd,cc,cb,ca: ad5 port e bit5 rw ....0110 cd,cc,cb,ca: ad6 port e bit6 rw ....0111 cd,cc,cb,ca: ad7 port e bit7 rw ....10xx cd,cc,cb,ca: reserved rw ....1100 cd,cc,cb,ca: Vref hi rw ....1101 cd,cc,cb,ca: Vref low rw ....1110 cd,cc,cb,ca: Vref hi/2 rw ....1111 cd,cc,cb,ca: test/reserved 1031 adr1 1032 adr2 1033 adr3 1034 adr4 1035 reserved 1036 reserved 1037 reserved 1038 reserved 1039 option: system configuration options w 1....... adpu: a->d system powered up/down w .1...... csel: a->d and ee use an internal-r-c/system-e clock w ..1..... irqe: irq configured for falling edges/low level w ...1.... dly: enable/disable oscillator start-up delay (from stop) w ....1... cme: slow or stopped clocks cause reset/disabled w .....x.. reserved w ......00 cr1,cr0: e/2^15 divided by 1 w ......01 cr1,cr0: e/2^15 divided by 4 w ......10 cr1,cr0: e/2^15 divided by 16 w ......11 cr1,cr0: e/2^15 divided by 64 103A coprst: arm/reset cop timer circuitry, write $55 and $aa to reset cop watchdog timer 103B pprog: eeprom programming register w 1....... odd: program odd rows in half of eeprom (test only) w .1...... even: program even rows in half of eeprom (test only) w ..x..... reserved w ...1.... byte: erase only one byte/row or all of eeprom w ....1... row: erase only one 16 byte row/all 512 bytes of eeprom w .....1.. erase: erase/normal read of program mode w ......1. eelat: eeprom busses configured for program or erase/read w .......1 eepgm: program or erase power switched on/off to program eeprom: * set eelat * write data to desired address * set eepgm for the required programming time to erase eeprom: * select row = 1/0 * select byte = 1/0 * set erase and eelat = 1 * write to an eeprom address to be erased * set eepgm for the required erase time period 103C hprio: highest priority interrupt and misc. w 1....... rboot: boot rom enabled/not in map (normal) w .00..... smod,mda: single chip mode w .01..... smod,mda: expanded multiplexed mode w .10..... smod,mda: special bootstrap w .11..... smod,mda: special test w ...1.... irv: data from internal reads visible/not on external bus reset to in test/boot mode: 1, in normal modes: 0 r ....0000 psel3,2,1,0: timer overflow r ....0001 psel3,2,1,0: pulse accum. overflow r ....0010 psel3,2,1,0: puls accum. input edge r ....0011 psel3,2,1,0: spi serial xfer complete r ....0100 psel3,2,1,0: sci serial system r ....0101 psel3,2,1,0: reserved (default to irq) r ....0110 psel3,2,1,0: irq (ext pin or parallel i/o r ....0111 psel3,2,1,0: real time interrupt r ....1000 psel3,2,1,0: timer input capture 1 r ....1001 psel3,2,1,0: timer input capture 2 r ....1010 psel3,2,1,0: timer input capture 3 r ....1011 psel3,2,1,0: timer output compare 1 r ....1100 psel3,2,1,0: timer output compare 2 r ....1101 psel3,2,1,0: timer output compare 3 r ....1110 psel3,2,1,0: timer output compare 4 r ....1111 psel3,2,1,0: timer output compare 5 103D init: ram and i/o mapping register w xxxx.... ram3,2,1,0: ram block position (x000..x0ff) w ....xxxx reg3,2,1,0: register block position (x000..x03f) 00000001 at reset 103E test1: factory test register w 1....... tilop: test illegal opcode w .x...... reserved w ..1..... occr: output condition code register status to timer port w ...1.... cbyp: timer divider chain bypass w ....1... disr: disable resets from cop and clock monitor w .....1.. fcm: force clock monitor failure w ......1. fcop: force cop watchdog failure w .......1 tcon: test configuration 103F config: configuration control register w ....1... nosec: dis/enable security mode (security only if mask option) w .....1.. nocop: dis/enable cop system w ......1. romon: en/disable rom at $e000..$ffff w .......1 eeon: en/disable eeprom at $b600..$b7ff note: The bits of this register are implemented with eeprom cells. programming and erasure follow normal eeprom procedures. The erased state of this location is $0f. A new value programmed into this register is not readable until after a subsequent reset sequence.
